1. Field of the Invention
The present invention relates to a processor unit for executing a plurality of processes based on priority levels assigned to the processes.
2. Related Art
In an electronic control unit (ECU) installed in a vehicle, some processes included in its control program should be executed in real time for providing the sufficient responsiveness of control and a driver's safety. Accordingly, the control program includes a plurality of processes each of which is a run unit, and one of three priority levels is assigned to each of the processes. Specifically, the control program is composed of three tasks, that is, a high priority task, a moderate priority task, and a low priority task, and the processes are divided into the three tasks. The control program is executed switching among the tasks, so that higher priority processes are preferentially executed. Thus the high priority processes are executed in real time.
In this case, if processes that have the different priority levels manipulate the same memory area, these processes would interfere with one another as follows. Referring to FIG. 5, a process of lower priority reads one byte (eight bit) data “0000 0000” from the shared memory area at step A. Thereafter switching from the lower priority task to the higher priority task is performed, and a process of higher priority reads the one byte data “0000 0000” from the shared memory area at step C. Then the higher priority process manipulates the data “0000 0000” (i.e., set the least significant bit (LSB)), and writes the resultant data “0000 0001” to the shared memory area at step D. Thereafter the lower priority process manipulates the retrieved data “0000 0000” (i.e., set the second LSB), and writes the resultant data “0000 0010” to the shared memory area at step B. Thus the lower priority process overwrites or resets the LSB that has been set by the higher priority process.
Further, in the case that the lower priority process repeatedly reads data from the shared memory area, the data to be read by the lower priority process changes halfway if the higher priority process writes data to the shared memory area in between times.
The ECU usually has a self-diagnostic feature for automatically checking the operating state of computers and sensors included therein at appropriate intervals. If a failure is detected, information on the failure is stored so that the garage mechanic in charge can know the type of the failure.
The failure detection is performed for various sensors such as a crank angle sensor, a cam angle sensor, and a coolant temperature sensor. The subjects for failure detection number almost 200. Therefore, if memory areas are allocated for storing failure information corresponding to the respective subjects by the byte, the large amount of memory area is required in total. Accordingly it is preferable that memory areas are allocated by the bit for effective use of resources.
However, the ECU usually employs a reduced instruction set computer (RISC) which does not have a bit manipulation instruction. Therefore, in the ECU, memory areas are allocated for storing failure information by the bit, but memory manipulation is performed by the byte. Accordingly, there is every possibility that a plurality of processes manipulate the same memory area, and therefore there is every possibility that the processes interfere with one another.
Then, in order to overcome such interference, it is proposed that switching from the lower priority task to the higher priority task is inhibited while the lower priority process performs memory manipulation. In this case, all the higher priority processes are inhibited from being executed interrupting the execution of the lower priority process while the lower priority process performs the memory manipulation. That is, even higher priority processes that do not interfere with the lower priority process are inhibited from interrupting the execution of the lower priority process while the lower priority process performs the memory manipulation. Accordingly execution of high priority processes which should be executed in real time would be delayed, and therefore the sufficient responsiveness of control or a driver's safety is not ensured in this case.